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| august 8 , 2012 | advanced datasheet | v 2. 1 | pd97603 1 ir347 6 1 2 a highly integrated supirbuck tm features ? input voltage r ange: 3v to 27 v ? output voltage range: 0.5v to 12v ? continuous 1 2 a load capability ? constant on - time control ? compensation loop not required ? excellent efficiency at very low output currents ? programmable switching frequency and soft s tart ? thermally compensated over current protection ? power good output ? precision voltage reference (0.5v, +/ - 1%) ? enable input with voltage monitoring capability ? pre - bias start up ? thermal shut down ? under/over voltage fault protection ? forced continuous co nduction mode option ? small, l ow profile 5mm x 6mm qfn package basic application figure 1: ir 3476 basic application circuit description the ir 3476 supirbuck tm is an easy - to - use, fully integrated and highly efficient dc/dc voltage regulator. th e onboard constant on time hysteretic controller and mosfets make ir 3476 a space - efficient solution that delivers up to 12a of precisely controlled output voltage. programmable switching frequency, soft start, and thermally compensated over current protect ion allows for a very flexible solution suitable for many different applications and an ideal choice for battery powered applications. additional features include pre - bias startup, very precise 0.5v reference, under/over voltage shutdown, thermal protectio n, power good output, and enable input with voltage monitoring capability. applications ? notebook and desktop computers ? consumer electronics C stb, lcd, tv, printers ? 12v and 24v distributed power systems ? general purpose pol dc - dc converters ? game consoles and graphics cards efficiency figure 2 : ir 3476 efficiency 45% 55% 65% 75% 85% 95% 0.01 0.1 1 10 100 load current (a) efficiency 12vin 8vin 19vin
august 8 , 2012 | advanced datasheet | v 2. 1 | pd97603 2 ir347 6 1 2 a highly integrated supirbuck tm ordering information ir 3476 D ? ? ? ? ? ? ? marking in formation package tape & reel qty part number m 750 ir 3476 m tr1pbf m 4 000 ir 347 6 mtrpbf pin diagram pbf C lead free tr C tape and reel m C package ty pe 3476 m ?yww ? xxxxx site/date/marking code lot code pin 1 identifier w c w c o pcb j o ja / 2 / 30 - ? ? ? ? august 8 , 2012 | advanced datasheet | v 2. 1 | pd97603 3 ir347 6 1 2 a highly integrated supirbuck tm functional block dia gram figure 3 : ir 3476 functional block diagram august 8 , 2012 | advanced datasheet | v 2. 1 | pd97603 4 ir347 6 1 2 a highly integrated supirbuck tm typ ical application figure 4 : demoboard schematic for vout = 1.05v, f s = 300khz demoboard bill o f materials qty reference designator value description manufacturer part number 3 c1, c21, c25 1.00uf capacitor, x7r, 1.00uf, 25v, 0.1, 0603 murata grm188r71e105ka12d 1 c10 47uf capacitor, 47uf, 6.3v, 805 tdk c2012x5r0j476m 2 c12, c20 0.100uf capacitor , x7r, 0.100uf, 50v, 0.1, 603 tdk c1608x7r1h104k 1 c2 22.0uf capacitor, x5r, 22.0uf, 16v, 20%, 1206 taiyo yuden emk316bj226ml - t 1 c3 68uf capacitor, electrolytic, 68uf, 25v, 0.2, smd panasonic eev - fk1e680p 1 c4 0.22uf capacitor, y5v, 0.22uf, 50v, - 20%, +80%, 0603 mur ata grm188f51h224za01d 1 c9 330uf capacitor, 330uf, 2 .5v, smd sanyo 2r5tpe330m9 1 l1 1.5uh inductor, ferrite, 1.5uh, 16.0a, 3.8mohm, smt cyntec pimb104t - 1r5ms - 39 3 r1, r2, r5 10.0k resistor, thick film, 10.0k, 1/10w, 0.01, 0603 koa rk73h1j 1002f 1 r3 200k resistor, thick film, 200k, 1/10w, 0.01, 603 koa rk73h1jltd2003f 1 r4 10.5k resistor, thick film, 10.5k, 1/10w, 0.01, 603 koa rk73h1jltd1052f 1 r7 2.80k resistor, thick film, 2.80k, 1/10w, 0.01, 603 koa rk73h1jltd2801f 1 r8 2.55k resist or, thick film, 2.55k, 1/10w, 0.01, 0603 koa rk73h1j2551f 1 sw1 switch switch, dip, spst, 2 position, smt c&k components sd02h0sk 1 u1 ir 3476 5mm x 6mm qfn irf ir 3476 mtrpbf vout tp7 tp10 en vcc tp23 +vsws tp24 +vsws +vins r12 open c26 open tp8 vouts 1 3 4 5 2 tp21 -vsws tp25 -vin1s c27 open tp12 vsws 1 3 4 5 2 tp22 +vsws vin c7 open c8 open c9 330uf c10 47uf -vout1s c11 open -vdd2s -vdd1s c1 1uf r7 2.80k r8 2.55k c12 0.1uf pgood c24 open iset -vout1s +vdd2s vout +vdd1s +3.3v +vin1s tp6 pgnds tp14 +3.3v u1 ir3476 3vcbp 8 fccm 1 ss 6 pgood 3 ff 15 gnd1 4 fb 5 gnd 17 nc1 7 iset 2 boot 14 vin 13 vcc 10 nc2 9 pgnd 11 phase 12 en 16 c4 0.22uf vcc tp4 en sw1 en / fccm 1 2 4 3 tp17 pgnd c20 0.1uf tp26 agnd c5 open vsw c21 1uf tp11 pgood l1 1.5uh r6 open c22 open tp1 vins r4 10.5k r3 200k c13 open c2 22uf c16 open + c3 68uf tp2 vin tp5 pgnd c14 open c17 open c18 open tp16 vcc fb r5 10k c15 open c6 open tp18 voltage sense +vins 1 +vdd1s 2 +vdd2s 3 +vout1s 4 +vout2s 5 -vout2s 10 -vdd2s 8 -vout1s 9 -vins 6 -vdd1s 7 -vout1s tp9 +vout1s r1 10k fccm +vin1s tp20 +vin1s +3.3v c25 1uf +vdd1s -vdd1s r13 open +3.3v tp15 -vout1s r14 open tp19 fb r11 open tp13 ss vsw +vdd2s tp3 fccm ss -vdd2s r2 10k ir3476 c19 open -vins pgnd vout c23 open august 8 , 2012 | advanced datasheet | v 2. 1 | pd97603 5 ir347 6 1 2 a highly integrated supirbuck tm pin descriptions pin # pin name i/o level pin description 1 fccm 3.3v forced continuous conduction mode (ccm). ground this pin to enable diode emulation mode or discontinuous conduction mode (dcm). pull this pin to 3.3v to operate in ccm under all load conditions. 2 iset connecting resistor to phase pin sets over current trip poi nt. 3 pgood 5v power good open drain output C pull up with a resistor to 3.3v 4, 17 gnd reference bias return and signal reference. 5 fb 3.3v inverting input to pwm comparator, ovp / pgood sense. 6 ss 3.3v soft start/shutdown. this pin provides user pr ogrammable soft - start function. connect an external capacitor from this pin to gnd to set the startup time of the output voltage. the converter can be shutdown by pulling this pin below 0.3v. 7 nc - - 8 3vcbp 3.3v for internal ldo. byp ass with a 1.0f ca pacitor to gnd. 9 nc - - 10 vcc 5v vcc input . gate drive supply. a minimum of 1.0f ceramic capacitor is required. 11 pgnd reference power return. 12 phase vin phase node (or switching node) of mosfet half bridge. 13 vin vin input voltage for the sys tem. 14 boot vin + vcc bootstrapped gate drive supply C connect a capacitor to phase. 15 ff vin input voltage feed forward C sets on - time with a resistor to vin. 16 en 5v enable pin to turn on and off the device. use two external resistors to set the tu rn on threshold (see electrical specifications ) for input voltage monitoring. august 8 , 2012 | advanced datasheet | v 2. 1 | pd97603 6 ir347 6 1 2 a highly integrated supirbuck tm absolute maximum rat ings stressesbeyondthoselistedunderbsolutemaximumratingsmaycausepermanentdamagetothedevice.theseare stress ratings only and function al operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. vin, ff - 0.3v to 30 v vcc, pgood, en - 0.3v to 8 v boot - 0.3v to 38 v phase - 0.3v to 30 v (dc), - 5 v (100ns) boot to phase - 0.3v to 8 v iset - 0.3v to 30 v , 30ma pgnd to gnd - 0.3v to +0.3 v all other pins - 0.3v to 3.9 v storage temperature range - 65c to 150c junction temperature range - 40c to 150c esd classification jedec class 1c mois ture sensitivity level jedec level 2 @ 260c (note 2) august 8 , 2012 | advanced datasheet | v 2. 1 | pd97603 7 ir347 6 1 2 a highly integrated supirbuck tm electrical specifica tions recommended operatin g conditions for rel iable operation with margin symbol min max units recommended vin range vin 3 27 * v recommended vcc range vcc 4.5 5.5 recommen ded output voltage range v out 0.5 12 recommended output current range i out 0 12 a recommended switching frequency f s n/a 750 khz recommended operating junction temperature t j - 40 125 c * phase pin must not exceed 30v. e lectrical characteri stics unles sotherwisespecified,thesespecificationsapplyovervin=12v,4.5v august 8 , 2012 | advanced datasheet | v 2. 1 | pd97603 9 ir347 6 1 2 a highly integrated supirbuck tm typical operating da ta tested with demoboard shown in figu re 4 , vin = 12v, vcc = 5v, vout = 1.05v, fs = 300khz, t a = 25 o c, no airflow, unless otherwise specified. figure 5 : efficiency vs. load current for vout = 1.05v figure 7: switching frequency vs. load current figure 9: load regulation figure 6: efficiency vs. load current for vin = 12v figure 8: r ff vs. switching frequency figure 10: line regulation at i out = 12a 0 50 100 150 200 250 300 350 400 0 3 6 9 12 load current (a) switching frequency (khz) 0 200 400 600 800 1000 1200 1400 200 250 300 350 400 450 500 550 600 650 700 750 switching frequency (khz) rff (kohm) 5.0 vout 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 1.050 1.052 1.054 1.056 1.058 1.060 8 9 10 11 12 13 14 15 16 17 18 19 input voltage (v) output voltage (v) 1.050 1.052 1.054 1.056 1.058 1.060 0 2 4 6 8 10 12 load current (a) output voltage (v) 12vin 8vin 19vin 50% 60% 70% 80% 90% 100% 0.01 0.1 1 10 100 load current (a) efficiency vout = 1.05v; l = 1.5 h, 3.8m vout = 1.5v; l = 2.2 h, 4.6m vout = 3.3v; l = 3.3 h, 7.7m 45% 55% 65% 75% 85% 95% 0.01 0.1 1 10 100 load current (a) efficiency 12vin 8vin 19vin august 8 , 2012 | advanced datasheet | v 2. 1 | pd97603 10 ir347 6 1 2 a highly integrated supirbuck tm typical operating da ta tested with demoboard shown in figure 4 , vin = 12v, vcc = 5v, vout = 1.05v, fs = 300khz, t a = 25 o c, no airflow, unless otherwise specified . figure 11 : startup figure 1 3 : dcm (i out = 0.1a) figure 1 5 : over current protection (tested by shorting vout to pgnd) figure 12 : shutdown figure 1 4 : ccm (i out = 12a) figure 1 6 : over voltage protection (teste d by shorting fb to vout) en pgood ss vout en pgood ss vout 5v/div 5v/div 1v/div 500mv/div 5ms/div 5v/div 5v/div 1v/div 500mv/div 500s/div vou t phase il 20mv/div 5v/div 5a/div 10s/div 20mv/div 5v/div 10a/div 2s/div 5v/div 1v/div 1v/div 10a /div 2 ms/div 5v/div 1v/div 500m v/div 2a /div 50 s/div vout phase il pgo od ss vout il pgood fb vout il august 8 , 2012 | advanced datasheet | v 2. 1 | pd97603 11 ir347 6 1 2 a highly integrated supirbuck tm typical operating da ta tested with demoboard shown in figure 4 , vin = 12v, vcc = 5v, vout = 1.05v, fs = 300khz, t a = 25 o c, no airflow, unless otherwise specified . figure 1 7 : load transient 0 - 8a figure 19 : dcm/fccm transition figure 21 : thermal image at vin = 12v, i out = 12a (ir 3476 : 98 o c, inductor: 58 o c, pcb: 4 7 o c) figure 1 8 : load transient 4 - 12a figure 20 : fccm/dcm transition figure 22 : thermal image at vin = 19v, i out = 12a (ir 3476 : 1 04 o c, inductor: 61 o c, pcb: 50 o c) vout phase il 50m v/div 10 v/div 5a /div 20 s/div vout phase il fccm phase vout il fccm phase vout il 5 0m v/div 10v/div 5a/div 20 s/div 5v/div 10v/div 500m v/div 5a /div 10 s/div 2 v/div 10 v/div 500m v/div 5 a /div 5 s/div august 8 , 2012 | advanced datasheet | v 2. 1 | pd97603 12 ir347 6 1 2 a highly integrated supirbuck tm theory of operation pwm comparator the pwm comparator initiates a set signal (pwm pulse) when the fb pin falls below the reference (vr ef) or the soft start (ss) voltage. on - time generator the pwm on - time duration is programmed with an external resistor (r ff ) from the input supply (vin) to the ff pin. the simplified equation for r ff is shown in equation 1. the ff pin is held to an inte rnal reference after en goes high. a copy of the current in r ff charges a timing capacitor, which sets the on - time duration, as shown in equation 2. control logic the control logic monitors input power sources, sequences the converter through the soft - start and protective modes, and initiates an internal run signal when all conditions are met. vcc and 3vcbp pins are continuously monitored, and the ir3476 will be disabled if the voltage of either pin drops below the falling thresholds. en_delay will be come high when vcc and 3vcbp are in the normal operating range and the en pin = high. soft start with en = high, an internal 10a current source charges the external capacitor (c ss ) on the ss pin to set the output voltage slew rate during the soft start i nterval. the soft start time (t ss ) can be calculated from equation 3. the feedback voltage tracks the ss pin until ss reaches the 0.5v reference voltage (vref), then feedback is regulated to vref. c ss will continue to be charged, and when ss pin reaches v ss (see electrical specification ), ss_delay goes high. with en_delay = low, the capacitor voltage and ss pin is held to the fb pin voltage. a normal startup sequence is shown in figure 2 3 . pgood the pgood pin is open drain and it needs to be externally p ulled high. high state indicates that output is in regulation. the pgood logic monitors en_delay, ss_delay, and under/over voltage fault signals. pgood is released only when en_delay and ss_delay = high and output voltage is within the ov and uv thresholds . pre - bias startup ir3476 is able to start up into pre - charged output, which prevents oscillation and disturbances of the output voltage. with constant on - time control, the output voltage is compared with the soft start voltage (ss) or vref, depending on w hich one is lower, and will not start switching unless the output voltage drops below the reference. this scheme prevents discharge of a pre - biased output voltage. shutdown the ir3476 will shutdown if vcc is below its uvlo limit. the ir3476 can be shutdown by pulling the en pin below its lower threshold. alternatively, the output can be shutdown by pulling the soft start pin below 0.3v. figure 23 : normal startup (1) f 20 1 v r sw out ff ? ? ? pf v (2) v 20 1 r t in ff on pf v ? ? ? (3) a 10 5 . 0 ? v c t ss ss ? ? august 8 , 2012 | advanced datasheet | v 2. 1 | pd97603 13 ir347 6 1 2 a highly integrated supirbuck tm under/over voltage m onitor the ir3476 monitors the voltage at the fb node through a 350ns f ilter. if the fb voltage is below the under voltage threshold, uv# is set to low holding pgood to be low. if the fb voltage is above the over voltage threshold, ov# is set to low, the shutdown signal (sd) is set to high, mosfet gates are turned off, and pg ood signal is pulled low. toggling vcc or en will allow the next start up. figure 24 and 25 show pgood status change when uv/ov is detected. the over voltage and under voltage thresholds can be found in the electrical specification section. * typical filter delay figure 24 : under/over voltage monitor * typical filter delay figure 25 : over voltage protection over current monitor the over - current circuitry monitors the output current duri ng each switching cycle. the voltage across the lower mosfet, vphase, is monitored for over current and zero crossing. the ocp circuit evaluates vphase for an over current condition typically 270ns after the lower mosfet is gated on. this delay functions t o filter out switching noise. the minimum lower gate interval allows time to sample vphase . the over current trip point is programmed with a resistor from the iset pin to phase pin, as shown in equation 4. when over current is detected, the mosfet gates a re tri - state and ss voltage is pulled to 0v. this initiates a new soft start cycle. if there is a total of four oc events, the ir3476 will disable switching. toggling vcc or en will allow the next start up. figure 2 6 : over current protection under voltage lock - out the ir3476 has vcc and en under voltage lock - out (uvlo) protection. when either vcc or en is below their uvlo threshold, ir3476 is disabled. ir3476 will restart when both vcc and en are above their uvlo thr esholds. over temperature pro tection when the ir3476 exceeds its over temperature threshold, the mosfet gates are tri - state and pgood is pulled low. switching resumes once temperature drops below the over temperature hysteresis level. (4) 19 i r r oc dson set a ? ? ? august 8 , 2012 | advanced datasheet | v 2. 1 | pd97603 14 ir347 6 1 2 a highly integrated supirbuck tm gate drive logic th e gate drive logic features adaptive dead time, diode emulation, and a minimum lower gate interval. an adaptive dead time prevents the simultaneous conduction o f the upper and lower mosfets. the lower gate voltage must be below approximately 1v after pwm goes high before the upper mosfet can be gated on. also, the differential voltage between the upper gate and phase must be below approximately 1v after pwm goes low before the lower mosfet can be gated on. the upper mosfet is gated on after the adaptive d elay for pwm = high and the lower mosfet is gated on after th e adaptive delay for pwm = low. when fccm = low, thelowermosfetisdrivenoffwhenthezcrosssignal indicates that the inductor current is about to reverse direction. the zcross comparator monitors the phase voltage to determine when to turn off the lower mosfet. thelowermosfetstaysoffuntilthenextpwmfalling edge. when the lower peak of the inductor current is above zero, ir3476 operates in continuous conduction mode. the continuou s conduction mode can also be selected for all load current levels by pulling fccm to high. whenevertheuppermosfetisturnedoff,itstays offforthe min off time denoted in the electrical specifications . this minimum duration allows time to recha rge the bootstrap capacitor and allows the over current monitor to sample the phase voltage. component selection selection of components for the converter is an iterative process which involves meeting the specifications and tradeoffs between performance and cost. the following sections will guide one through the process. inductor selection inductor selection involves meeting the steady state output ripple requirement, minimizing the switching loss of the upper mosfet, meeting transient response specifi cations and min imizing the output capacitance. the output voltage includes a dc voltage and a small ac ripple component due to the low pass filter which has incomplete attenuation of the switching harmonics. neglecting the inductance in series with the ou tput capacitor, the magnitude of the ac voltage ripple is determined by the total inductor ripple current flowing through the total equivalent series resistance (esr) of the output capacitor bank. one can use equation 5 to find the required inductance. i is defined as shown in figure 27 . the main advantage of small inductance is increased inductor current slew rate during a load transient, which leads to a smaller output capacitance requirement as discussed in the output capacitor selection section. th e draw back of using smaller inductances is increased switching power loss in the upper mosfet, which reduces the system efficiency and increases the thermal dissipation. f igure 27: typical input current waveform input capacitor selection the main fun ction of the input capacitor bank is to provide the input ripple current and fast slew rate current during the load current step up. the input capacitor bank must have adequate ripple current carrying capability to handle the total rms current. figure 27 s hows a typical input current. equation 6 shows the rms input current. the rms input current contains the dc load current and the inductor ripple current. as shown in equation 5 , the inductor ripple current is unrelated to the load current. the maximum rm s input current occurs at the maximum output current. the maximum power dissipation in the input capacitor equals the square of the maximum rms inputcurrenttimestheinputcapacitorstotalesr. the voltage rating of the input capacitor needs to be greater than the maximum input voltage because of high frequency ringing at the phase node. the typical percentage is 25%. ? ? (6) i i 3 1 1 fs t i dt t f ts 1 i 2 out on out ts 0 2 in_rms ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? (5) l 2 v v t i out in on ? ? ? ? august 8 , 2012 | advanced datasheet | v 2. 1 | pd97603 15 ir347 6 1 2 a highly integrated supirbuck tm output capacitor selection selection of the output capacitor requires meeting voltage overshoot requirements during load removal, a nd meeting steady state outpu t ripple voltage requirements. the output capacitor is the most expensive converter component and increases the overall system cost. the output capacitor decoupling in the converter typically includes the low frequency capaci tor, such as specialty polymer aluminum, and mid frequency ceramic capacitors. the first purpose of output capacitors is to provide current when the load demand exceeds the inductor current, as shown in figure 28. equation 7 shows the charge requirement f or a certain load step. the advantage provided by the ir3476 at a load step is the reduced delay compared to a fixed frequency control method. if the load increases right after the pwm signal goes low, the longest delay will be equal to the minimum lower gate on - time as shown in the electrical specification s section . the ir3476 also reduces the inductor current slew time, the time it takes for the inductor current to reach equality with the output current, by increasing the switching frequency up to 1/( t on + min off time ). this results in reduced recovery time. figure 28: charge requirement during load step the output voltage drop, v drop , initially depends on the character istic of the output capacitor. v drop is the sum of the equivalent series inductance (esl) of the output capacitor times the rate of change of the output current and the esr times the change of the output current. vesr is usually much greater than vesl. the ir3476 requires a total esr such that the ripple voltage at th e fb pin is greater than 7mv. the second purpose of the output capacitor is to minimize the overshoot of the output voltage when the load decreases as shown in figure 29 . by using the law of energy before and after the load removal, equation 8 shows the output capacitance requirement for a load step down. figure 29: typical output voltage response waveform boot capacitor selection the boot capacitor starts the cycle fully charged to a voltage of vb(0). cg equals 0.58nf in ir3476 . choose a suf ficientl ysmallvsuchthatvb(0) - vexceedsthe maximum gate threshold voltage to turn on the upper mosfet. choose a boot capacitor value larger than the calculated c boot in equation 9. equation 9 is based on charge balance at ccm operation. usually the boot capacitor will be discharged to a much lower voltage when the circuit is operating in dcm mode at light load, due to much longer lower mosfet off time and the bias current drawn by the ic. boot capacitance needs to be increased if insufficient turn - on of t he upper mosfet is observed at light load, typically larger than 0.1f is needed. the voltage rating of this part needs to be larger than vb(0) plus the desired derating voltage. it s esr and esl needs to be low in order to allow it to deliver the large c urrentanddi/dtswhich drive mosfets most efficiently. in support of these requirements a ceramic capacitor should be chosen. i out i step v out v l v esr v os v drop (8) v v i l c 2 out 2 os 2 step out ? ? ? (9) 1 v (0) v c c b g boot ? ? ? ? ? ? ? ? ? t l o a d c u r r e n t i s t e p i n d u c t o r s l e w r a t e o u t p u t c h a r g e t ? ? (7b) v v i l 2 1 v 1 c (7a) t i 0.5 v c q out in 2 step drop out step ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? august 8 , 2012 | advanced datasheet | v 2. 1 | pd97603 16 ir347 6 1 2 a highly integrated supirbuck tm design example design criteria ? input voltage, vin = 6v to 21v ? output voltage, vout = 1.25v ? switching frequency, fs = 400khz ? i n ductorripplecurrent,2i=3 ? maximum output current, iout = 12a ? over current trip, ioc = 18a ? current transient step size = 5a ? overshoot allowance, vos = vout + 50mv ? undershoot allowance, vdrop = 50mv find r ff : pickastandardvalue158k,1%resis tor. find rset: pick a 9.53 k,1%standardresistor. find a resistive voltage divider for v out = 1.25v: r 2 =1.33k,r 1 =1.96k,both1%standardresistors. choose the soft start capacitor: once the soft start time has chosen, such as 1000us to r each to the reference voltage, a 22nf for css is used to meet 1000us. choose an inductor to meet the design specification: choose the inductor with the lowest dcr and ac power loss as possible to increase the overall system efficiency. for insta nce, choose a pimb103e - 1r0ms - 39 manufactured by cyntec. the inductance of this part is 1h andhas2.7m dcr. ripple current needs to be recalculated using the chosen inductor. choose an input capacitor: a panasonic 10f (ecj3yb1e106m) accommodates 6 arms of ripple current at 300 k hz. due to the chemistry of multilayer ceramic capacitors, the capacitance varies over temperature and operating voltage, both ac and dc. one 10f capacitor is recommended. in a practical solution, one 1f capacitor is required along with 10f. the purpose of the 1f capacitor is to suppress the switching noise a nd deliver high frequency current. choose an output capacitor: to meet the undershoot and overshoot specification, equations 7b and 8 will be used to calculate the minimum output capacitance. as a result, 2 00 fwillbeneededfor5 load removal. to meet the stability requirement, choose an outputcapacitorwithesrlargerthan6m.combinethose two requirements, one can choose a set of output capacitors from manufactures such as sp - cap (specialty polymer cap acitor) from panasonic or poscap from sanyo. 220f ( eefsl0d221r ) from panasonic with9mesrwillmeetboth requirements. if an all ceramic output capacitor solution is desired, the external slope injection circuit composed of r6, c13, and c14 is requi red as explained in the stability consideration s s ection. in this design example, we can choose c14 = 1nf and c13 = 100nf. to calculate the value of r6 with pimb103e - 1r0ms - 39 as our inductor: pickastandardvalueforr6=3.74k. k 156 400k 20 1 1.25 r ff ? ? ? ? ? hz pf v v ? ? ? ? ? k 5 . 9 9 1 18 10m r set a a ? v 0.5 v r r r v out 1 2 2 fb ? ? ? ? ? ? ? ? h hz a v v v v ? 1.0 400k 3 21 1.25 - 21 1.25 f i 2 v v v v l s in out in out ? ? ? ? ? ? ? ? ? ? ? ? a hz h v v v v i 3 400k 1 21 1.25 - 21 1.25 2 ? ? ? ? ? ? a a a v v a 9 . 2 2 1 5 . 1 3 1 1 21 1.25 2 1 i 2 in_rms ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? k nf m h c dcr l r 7 . 3 100 7 . 2 1 13 6 ? august 8 , 2012 | advanced datasheet | v 2. 1 | pd97603 17 ir347 6 1 2 a highly integrated supirbuck tm stability considera tions con stant - on - time control is a fast , ripple based control scheme. unstable operation can occur if certain conditions are not met. the system instability is usually caused by: switching noise coupled to fb input: this causes the pwm comparator to tr igger prematurely after the 5 00ns minimum on - time for lower mosfet. it will result in double or multiple pulses every switching cycle instead of the expected single pulse. double pulsing can causes higher output voltage ripple, but in most application it will not affect operation. this can usually be prevented by careful layout of the ground plane and the fb sensing trace. steady state ripple on fb pin being too small: the pwm comparator in ir 3476 requires minimum 7mvp - p ripple voltage to operate stably . not enough ripple will result in similar double pulsing issue described above. solving this may require using output capacitors with higher esr. esr loop instability: the stability criteria of constant on - time is: if esr is too small that this crit eria is violated then sub - harmonic oscillation will occur. this is similar to the instability problem of peak - current - mode control with d>0.5. increasing esr is the most effective way to stabilize the system, but the tradeoff is the larger output voltage r ipple. system with all ceramic output capacitors: for applications with all ceramic output capacitors, the esr is usually too small to meet the stability criteria. in these applications, external slope compensation is necessary to make the loop stable. t he ramp injection circuit, composed of r6, c13, and c14, shown in figure 4 is required. the inductor current ripple sensed by r6 and c13 is ac coupled to the fb pin through c14. c14 is usually chosen between 1 to 10nf, and c13 between 10 to 100nf. r6 shou ld then be chosen such that l/dcr = c13*r6. layout recommendatio ns bypass capacitor: a 1f high quality ceramic capacitor should be placed on the same side as the ir3476 and connected to vcc and pgnd pins directly. boot circuit: c boot should be plac ed near the boot and phase pins to reduce the impedance when the upper mosfet turns on. power stage: figure 30 shows the current paths and their directions for the on and off periods. the on time path has low average dc current and high ac current. the refore, it is recommended to place the input ceramic capacitor, upper, and lower mosfet in a tight loop as shown in figure 30 . the purpose of the tight loop from the input ceramic capacitor is to suppress the high frequency (10mhz range) switching noise a nd reduce electromagnetic interference (emi). if this path has high inductance, the circuit will cause voltage spikes and ringing, and increase the switching loss. the off time path has low ac and high average dc current. therefore, it should be laid out with a tight loop and wide trace at both ends of the inductor. lowering the loop resistance reduces the po wer loss. the typical resistance value of 1 - ounce copper thickness is 0.5mpersquareinch. figure 30 : current path of power stag e q1 q2 2 on out t c esr ? ? august 8 , 2012 | advanced datasheet | v 2. 1 | pd97603 18 ir347 6 1 2 a highly integrated supirbuck tm pcb metal and component placement ? lead lands (the 13 ic pins) width should be equal to nominal part lead width. the mi nimum lead to leadspacingshouldbe0.2mmtominimize shorting . ? lead land length should be equal to maximum part lead length + 0.3 mm outboard extension. the outboard extension ensures a large toe fillet that can be easily inspected . ? pad lands (the 4 big pads) length and width should be equal to maximum part pad length and width. however, the minimum metal to metal spacing should be no less than; 0.17mm for 2 oz. copper or no less than 0.1mm for 1 oz. copper or no less than 0.23mm for 3 oz. copper . figure 31 : metal and c omponent p lacement * contact i nternational r ectifier to receive an electronic pcb library file in your preferred format august 8 , 2012 | advanced datasheet | v 2. 1 | pd97603 19 ir347 6 1 2 a highly integrated supirbuck tm solder resist ? it is recommended that the lead lands are non solder mask defined (nsmd). the solder resi st should be pulled away from the metal lead lands by a minimum of 0.025mm to ensure nsmd pads . ? the land pad should be solder mask defined (smd), with a minimum overlap of the solder resist onto the copper of 0.05mm to accommodate solder resist misalignme nt . ? ensure that the solder resist in between the lead landsandthepadlandis0.15mmduetothe high aspect ratio of the solder resist strip separating the lead lands from the pad land . figure 32 : solder r esist * contact i nternational r ecti fier to receive an electronic pcb library file in your preferred format august 8 , 2012 | advanced datasheet | v 2. 1 | pd97603 20 ir347 6 1 2 a highly integrated supirbuck tm stencil design ? the stencil apertures for the lead lands should be approximately 80% of the area of the lead lads. reducing the amount of solder deposited will minimize the occurrences of lead shorts. if too much solder is deposited on the center pad the part will float and the lead lands will open . ? the maximum length and width of the land pad stencil aperture should be equal to the solder resist opening minus an annular 0.2mm pull ba ck in order to decrease the risk of shorting the center land to the lead lands when the part is pushed into the solder paste . figure 33 : stencil d esign * contact i nternational r ectifier to receive an electronic pcb library file in your preferred form at august 8 , 2012 | advanced datasheet | v 2. 1 | pd97603 21 ir347 6 1 2 a highly integrated supirbuck tm package information figure 3 4 : p ackage d imensions data and specifications subject to change without notice. this product has been designed and qualified for the industrial m arket (note2) . qualificationstandardscanbefoundonirswebsite. ir world headquarters: 233 kansas st., el segundo, california 90245, usa tel: (310) 252 - 7105 tac fax: (310) 252 - 7903 visit us at www.irf.com for sales contact information www.irf.com |
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